File:FPGA cell example.png
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Size of this preview: 799 × 359 pixels. Other resolutions: 320 × 144 pixels | 957 × 430 pixels.
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| Date/Time | Thumbnail | Dimensions | User | Comment | |
|---|---|---|---|---|---|
| current | 17:20, 2 May 2010 | | 957 × 430 (7 KB) | commons>Petter.kallstrom | {{Information |Description={{en|1=An example of how an FPGA logic cell can look like, incl a 4 inp. LUT (or two 3-LUTs), a Full Adder and a D-type Flip Flop. The 2 muxes to the right have their select signal set during the programming of the cell.}} {{sv| |
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